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@clock-controller@3d900002qcom,x1e80100-gpucc{2=5=6fsiommu@3da0000B2qcom,x1e80100-smmu-500qcom,adreno-smmuqcom,smmu-500arm,mmu-5008>?@A {=7=87hlosbusifaceahbJsinterconnect@264000002qcom,x1e80100-gem-noc&@1&s?interconnect@320c00002qcom,x1e80100-nsp-noc2 &sremoteproc@68000002qcom,x1e80100-adsp-pas<R#wdogfatalreadyhandoverstop-ack{7xo;;lcxlmx{!stop0okay2qcom/x1e80100/adsp.mbnqcom/x1e80100/adsp_dtb.mbnglink-edgeR1 1%lpassfastrpc 2qcom,fastrpc+fastrpcglink-apps-dsp%adsp? compute-cb@32qcom,fastrpc-compute-cb)<<cJcompute-cb@42qcom,fastrpc-compute-cb)<<dJcompute-cb@52qcom,fastrpc-compute-cb)<<eJcompute-cb@62qcom,fastrpc-compute-cb)<<fJcompute-cb@72qcom,fastrpc-compute-cb)<<gJgpr 2qcom,gpr +adsp_appsVb service@1 2qcom,q6apmoavs/audiomsm/adsp/audio_pdsbedais2qcom,q6apm-lpass-daisosdais2qcom,q6apm-dais)<<aservice@2 2qcom,q6prmavs/audiomsm/adsp/audio_pdclock-controller2qcom,q6prm-lpass-clocksfscodec@6aa0000:2qcom,x1e80100-lpass-wsa-macroqcom,sm8550-lpass-wsa-macro({Dfg7mclkmacrodcodecfsgenf wsa2-mclkoWSA2ssoundwire@6ab00002qcom,soundwire-v2.0.0{7iface %WSA2eodefaultswr_audio_cgcr ??      & = X u o0okaysspeaker@0,02sdw20217020400eodefault [o WooferRight sspeaker@0,12sdw20217020400eodefault [o TweeterRight scodec@6ac000082qcom,x1e80100-lpass-rx-macroqcom,sm8550-lpass-rx-macro({@fg7mclkmacrodcodecfsgenfmclkossoundwire@6ad00002qcom,soundwire-v2.0.0{7iface %RXeodefaultswr_audio_cgcr        & = X u o0okayscodec@0,42sdw20217010d00scodec@6ae000082qcom,x1e80100-lpass-tx-macroqcom,sm8550-lpass-tx-macro({9fg7mclkmacrodcodecfsgenfmclkoscodec@6b00000:2qcom,x1e80100-lpass-wsa-macroqcom,sm8550-lpass-wsa-macro({Bfg7mclkmacrodcodecfsgenfmclkoWSAssoundwire@6b100002qcom,soundwire-v2.0.0{7iface %WSAeodefaultswr_audio_cgcr ??      & = X u o0okaysspeaker@0,02sdw20217020400eodefault [ o WooferLeft sspeaker@0,12sdw20217020400eodefault [ o TweeterLeft sclock-controller@6b6c00062qcom,x1e80100-lpassaudioccqcom,sc8280xp-lpassaudioccfssoundwire@6d300002qcom,soundwire-v2.0.0{7iface corewakeup%TXswr_audio_cgcreodefault&=Xu o0okayscodec@0,32sdw20217010d00scodec@6d4400082qcom,x1e80100-lpass-va-macroqcom,sm8550-lpass-va-macro@${9fg7mclkmacrodcodecffsgenoeodefault I>spinctrl@6e80000>2qcom,x1e80100-lpass-lpi-pinctrlqcom,sm8550-lpass-lpi-pinctrl %{fg 7coreaudio % 5 Astx-swr-active-statesclk-pins Mgpio0 Rswr_tx_clk [ j tdata-pins Mgpio1gpio2 Rswr_tx_data [ j rx-swr-active-statesclk-pins Mgpio3 Rswr_rx_clk [ j tdata-pins Mgpio4gpio5 Rswr_rx_data [ j dmic01-default-statesclk-pins Mgpio6 Rdmic1_clk [ data-pins Mgpio7 Rdmic1_data [ dmic23-default-statesclk-pins Mgpio8 Rdmic2_clk [ data-pins Mgpio9 Rdmic2_data [ wsa-swr-active-statesclk-pins Mgpio10 Rwsa_swr_clk [ j tdata-pins Mgpio11 Rwsa_swr_data [ j wsa2-swr-active-statesclk-pins Mgpio15 Rwsa2_swr_clk [ j tdata-pins Mgpio16 Rwsa2_swr_data [ j spkr-0-sd-n-active-state Mgpio12 Rgpio [ tsspkr-1-sd-n-active-state Mgpio13 Rgpio [ tsspkr-2-sd-n-active-state Mgpio17 Rgpio [ tsspkr-3-sd-n-active-state Mgpio18 Rgpio [ tsclock-controller@6ea0000,2qcom,x1e80100-lpassccqcom,sc8280xp-lpasscc fsinterconnect@7e400002qcom,x1e80100-lpass-ag-noc&interconnect@74000002qcom,x1e80100-lpass-lpiaon-noc@&interconnect@74300002qcom,x1e80100-lpass-lpicx-nocC&smmc@8804000&2qcom,x1e80100-sdhciqcom,sdhci-msm-v5@hc_irqpwr_irq{==7ifacecorexo )<  d, h;}0{ !?@Csdhc-ddrcpu-sdhc J 0disabledopp-table2operating-points-v2sopp-19200000=$Dopp-50000000=D/opp-100000000=D0opp-202000000= FDmmc@8844000&2qcom,x1e80100-sdhciqcom,sdhci-msm-v5@hc_irqpwr_irq{==7ifacecorexo )<` d, h;}0{ !?@Csdhc-ddrcpu-sdhc J 0disabledopp-table2operating-points-v2sopp-19200000=$Dopp-50000000=D/opp-100000000=D0opp-202000000= FDphy@88e000082qcom,x1e80100-snps-eusb2-phyqcom,sm8550-snps-eusb2-phyT{" 7ref=90okay eodefaultsphy@88e100082qcom,x1e80100-snps-eusb2-phyqcom,sm8550-snps-eusb2-phyT{"7ref=40okay sphy@88e200082qcom,x1e80100-snps-eusb2-phyqcom,sm8550-snps-eusb2-phy T{"7ref=50okay sphy@88e30002qcom,x1e80100-qmp-usb3-uni-phy0  {===7auxrefcom_auxpipe=G=L phyphy_phy=fusb_mp_phy0_pipe_clk0okay&sphy@88e50002qcom,x1e80100-qmp-usb3-uni-phyP  {===7auxrefcom_auxpipe=H=M phyphy_phy=fusb_mp_phy1_pipe_clk0okay&susb@a0f88002qcom,x1e80100-dwc3qcom,dwc3 H{====== ===R7cfg_noccoreifacesleepmock_utminoc_aggrnoc_aggr_northnoc_aggr_southnoc_sys==$ 4Rr:9 1pwr_eventdp_hs_phy_irqdm_hs_phy_irqss_phy_irq=D=A0{!?@%Cusb-ddrapps-usb  0okayusb@a000000 2snps,dwc3  a )< :usb2-phyusb3-phy    ' ?J Wotg _ports port@0endpointksport@1endpointksusb@a2f88002qcom,x1e80100-dwc3qcom,dwc3 / H{====== ===R7cfg_noccoreifacesleepmock_utminoc_aggrnoc_aggr_northnoc_aggr_southnoc_sys==$ (R21&pwr_eventdp_hs_phy_irqdm_hs_phy_irq=D==0{!?@"Cusb-ddrapps-usb o 0okayusb@a200000 2snps,dwc3   )< usb2-phy high-speed ' ?J Whostportendpointusb@a4f8800 2qcom,x1e80100-dwc3-mpqcom,dwc3 OH{====== ===R7cfg_noccoreifacesleepmock_utminoc_aggrnoc_aggr_northnoc_aggr_southnoc_sys==$ R9:58436578lpwr_event_1pwr_event_2hs_phy_1hs_phy_2dp_hs_phy_1dm_hs_phy_1dp_hs_phy_2dm_hs_phy_2ss_phy_1ss_phy_2=D=>0{!?@&Cusb-ddrapps-usb  0okayusb@a400000 2snps,dwc3 @ 3 )<usb2-0usb3-0usb2-1usb3-1 Whost    ' ?Jusb@a6f88002qcom,x1e80100-dwc3qcom,dwc3 oH{==== == ===R7cfg_noccoreifacesleepmock_utminoc_aggrnoc_aggr_northnoc_aggr_southnoc_sys==$ 4Rs=1pwr_eventdp_hs_phy_irqdm_hs_phy_irqss_phy_irq=D=?  0okayusb@a600000 2snps,dwc3 ` c )<  8usb2-phyusb3-phy    ' ?J Wotg _ports port@0endpointksport@1endpointksusb@a8f88002qcom,x1e80100-dwc3qcom,dwc3 H{== === = ===R7cfg_noccoreifacesleepmock_utminoc_aggrnoc_aggr_northnoc_aggr_southnoc_sys= = $ 4Rt< /1pwr_eventdp_hs_phy_irqdm_hs_phy_irqss_phy_irq=D=@0{!?@$Cusb-ddrapps-usb  0okayusb@a800000 2snps,dwc3  e )<` 9usb2-phyusb3-phy    ' ?J Wotg _ports port@0endpointksport@1endpointksvideo-codec@aa00000$2qcom,x1e80100-irisqcom,sm8550-iris   ; ;venusvcodec0mxcmmcx}{=Y7ifacecorevcodec0_core0{?@* !Ccpu-cfgvideo-mem =Xbus)<@<GJ0okayopp-table2operating-points-v2sopp-192000000= qD  opp-240000000=ND0/opp-338000000=%xD00opp-366000000=зDopp-444000000=vDopp-481000000=z@D  clock-controller@aaf00002qcom,x1e80100-videocc  {2=X;; D//fsdisplay-subsystem@ae000002qcom,x1e80100-mdss 6mdss S{ =& : H{ ? !!?@Cmdp0-memmdp1-memcpu-cfg  )< 0okaysdisplay-controller@ae010002qcom,x1e80100-dpu   6mdpvbifR({=&  = : F7nrt_busifacelutcorevsync};ports port@0endpointksport@4endpointksport@5endpointks!port@6endpointksopp-table2operating-points-v2sopp-200000000= D/opp-325000000=_@D0opp-375000000=Z Dopp-514000000=Dopp-575000000="EDdisplayport-controller@ae900002qcom,x1e80100-dpP     R 0{      J7core_ifacecore_auxctrl_linkctrl_link_ifacestream_pixelstream_1_pixel    888};8dpo0okayports port@0endpointksport@1endpoint k `=Av1sopp-table2operating-points-v2sopp-160000000= hD/opp-270000000=߀D0opp-540000000= /Dopp-810000000=0GDdisplayport-controller@ae980002qcom,x1e80100-dpP    R 0{      J7core_ifacecore_auxctrl_linkctrl_link_ifacestream_pixelstream_1_pixel    999};9dpo0okayports port@0endpointksport@1endpoint k `=Av1sopp-table2operating-points-v2sopp-160000000= hD/opp-270000000=߀D0opp-540000000= /Dopp-810000000=0GDdisplayport-controller@ae9a0002qcom,x1e80100-dpP    R0{  " $ ' ( *J7core_ifacecore_auxctrl_linkctrl_link_ifacestream_pixelstream_1_pixel % ) + :::};:dpo0okayports port@0endpointksport@1endpoint k `=Av1sopp-table2operating-points-v2sopp-160000000= hD/opp-270000000=߀D0opp-540000000= /Dopp-810000000=0GDdisplayport-controller@aea00002qcom,x1e80100-dpP     R({  - / 2 3;7core_ifacecore_auxctrl_linkctrl_link_ifacestream_pixel 0 4 };dp0okaye odefaultports port@0endpointk!sport@1endpoint  `=Av1k"s$opp-table2operating-points-v2sopp-160000000= hD/opp-270000000=߀D0opp-540000000= /Dopp-810000000=0GDaux-buspanel 2edp-panel #portendpointk$s"phy@aec2a002qcom,x1e80100-dp-phy@ * " & { " " 7auxcfg_ahbref;f 0disabledphy@aec5a002qcom,x1e80100-dp-phy@ Z R V P{ - " 7auxcfg_ahbref;f0okay&sclock-controller@af000002qcom,x1e80100-dispcc d{2%=%38899::;D/fs interrupt-controller@b2200002qcom,x1e80100-pdcqcom,pdc "@dH **/ 4ca  0spower-management@c300000%2qcom,x1e80100-aoss-qmpqcom,aoss-qmp 01R1 1fssram@c3f00002qcom,rpmh-stats ?arbiter@c4000002qcom,x1e80100-spmi-pmic-arb0 @0 P@ D6corechnlsobsrvr   spmi@c42d000 B@ L 6cnfgintr periph_irq R pmic@02qcom,pm8550qcom,spmi-pmic pon@13002qcom,pmk8350-pon 6hlospbspwrkey2qcom,pmk8350-pwrkey tresin2qcom,pmk8350-resin 0disabledrtc@61002qcom,pmk8350-rtcab 6rtcalarmb  nvram@71002qcom,spmi-sdamq  qreboot-reason@48H +nvram@7e002qcom,spmi-sdam~  ~charge-limit-en@73scharge-limit-end@75ucharge-limit-delta@76vgpio@8800!2qcom,pmk8550-gpioqcom,spmi-gpio % A& 5s&pwm2qcom,pmk8550-pwm 0 0disabledpmic@12qcom,pm8550qcom,spmi-pmic temp-alarm@a002qcom,spmi-temp-alarm  sgpio@8800 2qcom,pm8550-gpioqcom,spmi-gpio % A'  5s'rtmr0-reset-n-active-state Mgpio10 Rnormal ; t H Vusb0-3p3-reg-en-state Mgpio11 Rnormal ; t H Vsled-controller@ee00*2qcom,pm8550-flash-ledqcom,spmi-flash-led 0disabledpwm!2qcom,pm8550-pwmqcom,pm8350c-pwm 0 0disabledpmic@22qcom,pm8550qcom,spmi-pmic temp-alarm@a002qcom,spmi-temp-alarm  sgpio@8800"2qcom,pm8550ve-gpioqcom,spmi-gpio % A( 5s(pmic@32qcom,pmc8380qcom,spmi-pmic temp-alarm@a002qcom,spmi-temp-alarm  sgpio@8800!2qcom,pmc8380-gpioqcom,spmi-gpio % A)  5s)pmic@42qcom,pmc8380qcom,spmi-pmic temp-alarm@a002qcom,spmi-temp-alarm  sgpio@8800!2qcom,pmc8380-gpioqcom,spmi-gpio % A*  5s*pmic@52qcom,pmc8380qcom,spmi-pmic temp-alarm@a002qcom,spmi-temp-alarm  sgpio@8800!2qcom,pmc8380-gpioqcom,spmi-gpio % A+  5s+usb0-pwr-1p15-reg-en-state Mgpio8 Rnormal ; t H Vspmic@62qcom,pmc8380qcom,spmi-pmic temp-alarm@a002qcom,spmi-temp-alarm  sgpio@8800!2qcom,pmc8380-gpioqcom,spmi-gpio % A,  5s,pmic@82qcom,pm8550qcom,spmi-pmic temp-alarm@a002qcom,spmi-temp-alarm  sgpio@8800"2qcom,pm8550ve-gpioqcom,spmi-gpio % A- 5s-pmic@92qcom,pm8550qcom,spmi-pmic  temp-alarm@a002qcom,spmi-temp-alarm  sgpio@8800"2qcom,pm8550ve-gpioqcom,spmi-gpio % A. 5s.usb0-1p8-reg-en-state Mgpio8 Rnormal ; t H Vspmic@c2qcom,pm8010qcom,spmi-pmic   0disabledtemp-alarm@24002qcom,spmi-temp-alarm$ $sspmi@c432000 C @ M 6cnfgintr periph_irq R pmic@72qcom,smb2360qcom,spmi-pmic 0okayphy@fd002qcom,smb2360-eusb2-repeater d/ q0spmic@a2qcom,smb2360qcom,spmi-pmic  0okayphy@fd002qcom,smb2360-eusb2-repeater d/ q1spmic@b2qcom,smb2360qcom,spmi-pmic  0okayphy@fd002qcom,smb2360-eusb2-repeater d/ q2spmic@c2qcom,smb2360qcom,spmi-pmic   0disabledphy@fd002qcom,smb2360-eusb2-repeaterpinctrl@f1000002qcom,x1e80100-tlmm  % 5 A } "sedp0-hpd-default-state Mgpio119 Redp0_hot ts qup-i2c0-data-clk-state Mgpio0gpio1 Rqup0_se0 [ squp-i2c1-data-clk-state Mgpio4gpio5 Rqup0_se1 [ squp-i2c2-data-clk-state Mgpio8gpio9 Rqup0_se2 [ squp-i2c3-data-clk-state Mgpio12gpio13 Rqup0_se3 [ squp-i2c4-data-clk-state Mgpio16gpio17 Rqup0_se4 [ squp-i2c5-data-clk-state Mgpio20gpio21 Rqup0_se5 [ squp-i2c6-data-clk-state Mgpio24gpio25 Rqup0_se6 [ squp-i2c7-data-clk-state Mgpio14gpio15 Rqup0_se7 [ squp-i2c8-data-clk-state Mgpio32gpio33 Rqup1_se0 [ s_qup-i2c9-data-clk-state Mgpio36gpio37 Rqup1_se1 [ sbqup-i2c10-data-clk-state Mgpio40gpio41 Rqup1_se2 [ sequp-i2c11-data-clk-state Mgpio44gpio45 Rqup1_se3 [ shqup-i2c12-data-clk-state Mgpio48gpio49 Rqup1_se4 [ skqup-i2c13-data-clk-state Mgpio52gpio53 Rqup1_se5 [ snqup-i2c14-data-clk-state Mgpio56gpio57 Rqup1_se6 [ sqqup-i2c15-data-clk-state Mgpio54gpio55 Rqup1_se7 [ s|qup-i2c16-data-clk-state Mgpio64gpio65 Rqup2_se0 [ sBqup-i2c17-data-clk-state Mgpio68gpio69 Rqup2_se1 [ sFqup-i2c18-data-clk-state Mgpio72gpio73 Rqup2_se2 [ sIqup-i2c19-data-clk-state Mgpio76gpio77 Rqup2_se3 [ sMqup-i2c20-data-clk-state Mgpio80gpio81 Rqup2_se4 [ sPqup-i2c21-data-clk-state Mgpio84gpio85 Rqup2_se5 [ sSqup-i2c22-data-clk-state Mgpio88gpio89 Rqup2_se6 [ sWqup-i2c23-data-clk-state Mgpio86gpio87 Rqup2_se7 [ sZqup-spi0-cs-state Mgpio3 Rqup0_se0 [ tsqup-spi0-data-clk-state Mgpio0gpio1gpio2 Rqup0_se0 [ tsqup-spi1-cs-state Mgpio7 Rqup0_se1 [ tsqup-spi1-data-clk-state Mgpio4gpio5gpio6 Rqup0_se1 [ tsqup-spi2-cs-state Mgpio11 Rqup0_se2 [ tsqup-spi2-data-clk-state Mgpio8gpio9gpio10 Rqup0_se2 [ tsqup-spi3-cs-state Mgpio15 Rqup0_se3 [ tsqup-spi3-data-clk-state Mgpio12gpio13gpio14 Rqup0_se3 [ tsqup-spi4-cs-state Mgpio19 Rqup0_se4 [ tsqup-spi4-data-clk-state Mgpio16gpio17gpio18 Rqup0_se4 [ tsqup-spi5-cs-state Mgpio23 Rqup0_se5 [ tsqup-spi5-data-clk-state Mgpio20gpio21gpio22 Rqup0_se5 [ tsqup-spi6-cs-state Mgpio27 Rqup0_se6 [ tsqup-spi6-data-clk-state Mgpio24gpio25gpio26 Rqup0_se6 [ tsqup-spi7-cs-state Mgpio13 Rqup0_se7 [ tsqup-spi7-data-clk-state Mgpio14gpio15gpio12 Rqup0_se7 [ tsqup-spi8-cs-state Mgpio35 Rqup1_se0 [ tsaqup-spi8-data-clk-state Mgpio32gpio33gpio34 Rqup1_se0 [ ts`qup-spi9-cs-state Mgpio39 Rqup1_se1 [ tsdqup-spi9-data-clk-state Mgpio36gpio37gpio38 Rqup1_se1 [ tscqup-spi10-cs-state Mgpio43 Rqup1_se2 [ tsgqup-spi10-data-clk-state Mgpio40gpio41gpio42 Rqup1_se2 [ tsfqup-spi11-cs-state Mgpio47 Rqup1_se3 [ tsjqup-spi11-data-clk-state Mgpio44gpio45gpio46 Rqup1_se3 [ tsiqup-spi12-cs-state Mgpio51 Rqup1_se4 [ tsmqup-spi12-data-clk-state Mgpio48gpio49gpio50 Rqup1_se4 [ tslqup-spi13-cs-state Mgpio55 Rqup1_se5 [ tspqup-spi13-data-clk-state Mgpio52gpio53gpio54 Rqup1_se5 [ tsoqup-spi14-cs-state Mgpio59 Rqup1_se6 [ tssqup-spi14-data-clk-state Mgpio56gpio57gpio58 Rqup1_se6 [ tsrqup-spi15-cs-state Mgpio53 Rqup1_se7 [ ts~qup-spi15-data-clk-state Mgpio54gpio55gpio52 Rqup1_se7 [ ts}qup-spi16-cs-state Mgpio67 Rqup2_se0 [ tsEqup-spi16-data-clk-state Mgpio64gpio65gpio66 Rqup2_se0 [ tsDqup-spi17-cs-state Mgpio71 Rqup2_se1 [ tsHqup-spi17-data-clk-state Mgpio68gpio69gpio70 Rqup2_se1 [ tsGqup-spi18-cs-state Mgpio75 Rqup2_se2 [ tsLqup-spi18-data-clk-state Mgpio72gpio73gpio74 Rqup2_se2 [ tsKqup-spi19-cs-state Mgpio79 Rqup2_se3 [ tsOqup-spi19-data-clk-state Mgpio76gpio77gpio78 Rqup2_se3 [ tsNqup-spi20-cs-state Mgpio83 Rqup2_se4 [ tsRqup-spi20-data-clk-state Mgpio80gpio81gpio82 Rqup2_se4 [ tsQqup-spi21-cs-state Mgpio87 Rqup2_se5 [ tsUqup-spi21-data-clk-state Mgpio84gpio85gpio86 Rqup2_se5 [ tsTqup-spi22-cs-state Mgpio91 Rqup2_se6 [ tsYqup-spi22-data-clk-state Mgpio88gpio89gpio90 Rqup2_se6 [ tsXqup-spi23-cs-state Mgpio85 Rqup2_se7 [ ts\qup-spi23-data-clk-state Mgpio86gpio87gpio84 Rqup2_se7 [ ts[qup-uart2-default-statescts-pins Mgpio8 Rqup0_se2 [ trts-pins Mgpio9 Rqup0_se2 [ ttx-pins Mgpio10 Rqup0_se2 [ trx-pins Mgpio11 Rqup0_se2 [ tqup-uart14-default-statestcts-pins Mgpio56 Rqup1_se6 rts-pins Mgpio57 Rqup1_se6 [ ttx-pins Mgpio58 Rqup1_se6 [ trx-pins Mgpio59 Rqup1_se6 qup-uart21-default-statesVtx-pins Mgpio86 Rqup2_se5 [ trx-pins Mgpio87 Rqup2_se5 [ tsdc2-default-stateclk-pins Msdc2_clk [ tcmd-pins Msdc2_cmd [  data-pins Msdc2_data [  sdc2-sleep-stateclk-pins Msdc2_clk [ tcmd-pins Msdc2_cmd [ data-pins Msdc2_data [ pcie4-default-statesclkreq-n-pins Mgpio147 Rpcie4_clk [ perst-n-pins Mgpio146 Rgpio [ twake-n-pins Mgpio148 Rgpio [ pcie6a-default-statesclkreq-n-pins Mgpio153 Rpcie6a_clk [ perst-n-pins Mgpio152 Rgpio [ twake-n-pins Mgpio154 Rgpio [ edp-reg-en-state Mgpio70 Rgpio [ tseusb3-reset-n-state Mgpio6 Rgpio [ t seusb5-reset-n-state Mgpio7 Rgpio [  seusb6-reset-n-state Mgpio184 Rgpio [  snvme-reg-en-state Mgpio18 Rgpio [ tsrtmr1-reset-n-active-state Mgpio176 Rgpio [ tsrtmr2-reset-n-active-state Mgpio185 Rgpio [ tsusb1-pwr-1p15-reg-en-state Mgpio188 Rgpio [ tsusb1-pwr-1p8-reg-en-state Mgpio175 Rgpio [ tsusb1-pwr-3p3-reg-en-state Mgpio186 Rgpio [ tsusb2-pwr-1p15-reg-en-state Mgpio189 Rgpio [ tsusb2-pwr-1p8-reg-en-state Mgpio126 Rgpio [ tsusb2-pwr-3p3-reg-en-state Mgpio187 Rgpio [ tsusb-1-ss0-sbu-statesmode-pins Mgpio166 Rgpio t [ oe-n-pins Mgpio168 Rgpio t [sel-pins Mgpio167 Rgpio t [wcd-reset-n-active-state Mgpio191 Rgpio [ t swcn-bt-en-state Mgpio116 Rgpio [ tswwan-sw-en-state Mgpio221 Rgpio [ tswcn-sw-en-state Mgpio214 Rgpio [ tswcn-usb-sw-n-state Mgpio225 Rgpio [ t sstm@10002000 2arm,coresight-stmarm,primecell  (6stm-basestm-stimulus-base{ 7apb_pclkout-portsportendpointk3s:tpdm@10003000"2qcom,coresight-tpdmarm,primecell0{ 7apb_pclk   0disabledout-portsportendpointk4s5tpda@10004000"2qcom,coresight-tpdaarm,primecell@{ 7apb_pclkin-ports port@0endpointk5s4port@1endpointk6s8out-portsportendpointk7s9tpdm@1000f000"2qcom,coresight-tpdmarm,primecell{ 7apb_pclk  out-portsportendpointk8s6funnel@10041000+2arm,coresight-dynamic-funnelarm,primecell{ 7apb_pclkin-ports port@6endpointk9s7port@7endpointk:s3out-portsportendpointk;s@funnel@10042000+2arm,coresight-dynamic-funnelarm,primecell { 7apb_pclkin-ports port@2endpointk<sport@5endpointk=sPport@6endpointk>sxout-portsportendpointk?sAfunnel@10045000+2arm,coresight-dynamic-funnelarm,primecellP{ 7apb_pclkin-ports port@0endpointk@s;port@1endpointkAs?out-portsportendpointkBsStpdm@10800000"2qcom,coresight-tpdmarm,primecell{ 7apb_pclk @ out-portsportendpointkCs|tpdm@1082c000"2qcom,coresight-tpdmarm,primecell{ 7apb_pclk  out-portsportendpointkDsqtpdm@10841000"2qcom,coresight-tpdmarm,primecell{ 7apb_pclk  out-portsportendpointkEsotpdm@10844000"2qcom,coresight-tpdmarm,primecell@{ 7apb_pclk  out-portsportendpointkFsGfunnel@10846000+2arm,coresight-dynamic-funnelarm,primecell`{ 7apb_pclkin-portsportendpointkGsFout-portsportendpointkHsncti@1098b000 2arm,coresight-ctiarm,primecell{ 7apb_pclktpdm@109d0000"2qcom,coresight-tpdmarm,primecell{ 7apb_pclk   0disabledout-portsportendpointkIsptpdm@10ac0000"2qcom,coresight-tpdmarm,primecell{ 7apb_pclk   0disabledout-portsportendpointkJsLtpdm@10ac1000"2qcom,coresight-tpdmarm,primecell{ 7apb_pclk @ out-portsportendpointkKsMtpda@10ac4000"2qcom,coresight-tpdaarm,primecell@{ 7apb_pclkin-ports port@8endpointkLsJport@9 endpointkMsKout-portsportendpointkNsOfunnel@10ac5000+2arm,coresight-dynamic-funnelarm,primecellP{ 7apb_pclkin-portsportendpointkOsNout-portsportendpointkPs=funnel@10b04000+2arm,coresight-dynamic-funnelarm,primecell@{ 7apb_pclkin-ports port@3endpointkQshport@6endpointkRs^port@7endpointkSsBout-portsportendpointkTsUtmc@10b05000 2arm,coresight-tmcarm,primecellP{ 7apb_pclkin-portsportendpointkUsTout-portsportendpointkVsWreplicator@10b06000/2arm,coresight-dynamic-replicatorarm,primecell`{ 7apb_pclkin-portsportendpointkWsVout-portsportendpointkXstpda@10b08000"2qcom,coresight-tpdaarm,primecell{ 7apb_pclkin-ports port@0endpointkYs_port@1endpointkZs`port@2endpointk[saport@3endpointk\sbport@4endpointk]scout-portsportendpointk^sRtpdm@10b09000"2qcom,coresight-tpdmarm,primecell{ 7apb_pclk @ out-portsportendpointk_sYtpdm@10b0a000"2qcom,coresight-tpdmarm,primecell{ 7apb_pclk @ out-portsportendpointk`sZtpdm@10b0b000"2qcom,coresight-tpdmarm,primecell{ 7apb_pclk @ out-portsportendpointkas[tpdm@10b0c000"2qcom,coresight-tpdmarm,primecell{ 7apb_pclk @ out-portsportendpointkbs\tpdm@10b0d000"2qcom,coresight-tpdmarm,primecell{ 7apb_pclk  out-portsportendpointkcs]tpdm@10b20000"2qcom,coresight-tpdmarm,primecell{ 7apb_pclk   0disabledout-portsportendpointkdsetpda@10b23000"2qcom,coresight-tpdaarm,primecell0{ 7apb_pclk 0disabledin-portsportendpointkesdout-portsportendpointkfsgfunnel@10b24000+2arm,coresight-dynamic-funnelarm,primecell@{ 7apb_pclk 0disabledin-portsportendpointkgsfout-portsportendpointkhsQtpdm@10c08000"2qcom,coresight-tpdmarm,primecell{ 7apb_pclk  out-portsportendpointkisjfunnel@10c0b000+2arm,coresight-dynamic-funnelarm,primecell{ 7apb_pclkin-ports port@4endpointkjsiout-portsportendpointkks{tpdm@10c28000"2qcom,coresight-tpdmarm,primecell€{ 7apb_pclk  out-portsportendpointklsrtpdm@10c29000"2qcom,coresight-tpdmarm,primecell{ 7apb_pclk @ out-portsportendpointkmsstpda@10c2b000"2qcom,coresight-tpdaarm,primecell°{ 7apb_pclkin-ports port@4endpointknsHport@13endpointkosEport@14endpointkpsIport@15endpointkqsDport@1aendpointkrslport@1bendpointkssmout-portsportendpointktsufunnel@10c2c000+2arm,coresight-dynamic-funnelarm,primecell{ 7apb_pclkin-ports port@0endpointkustport@4endpointkvsport@5endpointkwsout-portsportendpointkxs>tpdm@10c38000"2qcom,coresight-tpdmarm,primecellÀ{ 7apb_pclk @ out-portsportendpointkys}tpdm@10c39000"2qcom,coresight-tpdmarm,primecellÐ{ 7apb_pclk @ out-portsportendpointkzs~tpda@10c3c000"2qcom,coresight-tpdaarm,primecell{ 7apb_pclkin-ports port@4endpointk{skport@fendpointk|sCport@10endpointk}syport@11endpointk~szout-portsportendpointksfunnel@10c3d000+2arm,coresight-dynamic-funnelarm,primecell{ 7apb_pclkin-portsportendpointksout-portsportendpointksvtpdm@10cc1000"2qcom,coresight-tpdmarm,primecell{ 7apb_pclk @    0disabledout-portsportendpointkstpda@10cc4000"2qcom,coresight-tpdaarm,primecell@{ 7apb_pclkin-ports port@2endpointksout-portsportendpointksfunnel@10cc5000+2arm,coresight-dynamic-funnelarm,primecellP{ 7apb_pclkin-portsportendpointksout-portsportendpointks<funnel@10d04000+2arm,coresight-dynamic-funnelarm,primecell@{ 7apb_pclkin-ports port@6endpointksout-portsportendpointkswtpdm@10d08000"2qcom,coresight-tpdmarm,primecellЀ{ 7apb_pclk  out-portsportendpointkstpdm@10d09000"2qcom,coresight-tpdmarm,primecellА{ 7apb_pclk  out-portsportendpointkstpdm@10d0a000"2qcom,coresight-tpdmarm,primecellР{ 7apb_pclk  out-portsportendpointkstpdm@10d0b000"2qcom,coresight-tpdmarm,primecellа{ 7apb_pclk  out-portsportendpointkstpdm@10d0c000"2qcom,coresight-tpdmarm,primecell{ 7apb_pclk  out-portsportendpointkstpdm@10d0d000"2qcom,coresight-tpdmarm,primecell{ 7apb_pclk  out-portsportendpointkstpdm@10d0e000"2qcom,coresight-tpdmarm,primecell{ 7apb_pclk  out-portsportendpointkstpdm@10d0f000"2qcom,coresight-tpdmarm,primecell{ 7apb_pclk  out-portsportendpointkstpda@10d12000"2qcom,coresight-tpdaarm,primecell { 7apb_pclkin-ports port@0endpointksport@1endpointksport@2endpointksport@3endpointksport@4endpointksport@5endpointksport@6endpointksport@7endpointksout-portsportendpointksfunnel@10d13000+2arm,coresight-dynamic-funnelarm,primecell0{ 7apb_pclkin-portsportendpointksout-portsportendpointksiommu@1500000012qcom,x1e80100-smmu-500qcom,smmu-500arm,mmu-500Aabcdefghijklmnopqrstuv;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYJs<iommu@15400000 2arm,smmu-v3@$eventqgerrorcmdq-syncJ 0reservedinterrupt-controller@17000000 2arm,gic-v3 0     smsi-controller@170400002arm,gic-v3-its 4 Csmailbox@174300002qcom,x1e80100-cpucp-mbox C s#rsc@175000002qcom,rpmh-rsc0PQR6drv-0drv-1drv-2$ N  ^ j %apps_rsc-bcm-voter2qcom,bcm-voters&clock-controller2qcom,x1e80100-rpmh-clk{7xofspower-controller2qcom,x1e80100-rpmhpd}s;opp-table2operating-points-v2sopp-16opp-480sopp-524opp-568s opp-60<opp-64@s/opp-80Popp-128s0opp-144opp-192sopp-256sopp-320@sopp-336Popp-384s opp-416regulators-02qcom,pm8550-rpmh-regulators zb          $bob1 3vreg_bob1 B- Zopp-1q@opp-2|opp-3opp-4Ȁopp-5`@pmu@240b6400*2qcom,x1e80100-cpu-bwmonqcom,sdm845-bwmon$ d E{?? }system-cache-controller@250000002qcom,x1e80100-llcc% % %@ %` % % % % & & 6llcc0_basellcc1_basellcc2_basellcc3_basellcc4_basellcc5_basellcc6_basellcc7_basellcc_broadcast_basellcc_broadcast_and_base  remoteproc@323000002qcom,x1e80100-cdsp-pas20@RB#wdogfatalreadyhandoverstop-ack{7xo;; ;  cxmxcnsp{!stop0okay2qcom/x1e80100/cdsp.mbnqcom/x1e80100/cdsp_dtb.mbnglink-edgeR1 1%cdspfastrpc 2qcom,fastrpc+fastrpcglink-apps-dsp%cdsp? compute-cb@12qcom,fastrpc-compute-cb )<  Jcompute-cb@22qcom,fastrpc-compute-cb )<  Jcompute-cb@32qcom,fastrpc-compute-cb )<  Jcompute-cb@42qcom,fastrpc-compute-cb )<  Jcompute-cb@52qcom,fastrpc-compute-cb )<  Jcompute-cb@62qcom,fastrpc-compute-cb )<  Jcompute-cb@72qcom,fastrpc-compute-cb )<  Jcompute-cb@82qcom,fastrpc-compute-cb )<  Jcompute-cb@102qcom,fastrpc-compute-cb  )< Jcompute-cb@112qcom,fastrpc-compute-cb  )< Jcompute-cb@122qcom,fastrpc-compute-cb  )<  Jcompute-cb@132qcom,fastrpc-compute-cb  )<  Jtimer2arm,armv8-timer0   thermal-zonesaoss0-thermal tripstrip-point0_(Ehotaoss0-critical8( Ecriticalcpu0-0-top-thermal tripscpu-critical8( Ecriticalcpu0-0-btm-thermal tripscpu-critical8( Ecriticalcpu0-1-top-thermal tripscpu-critical8( Ecriticalcpu0-1-btm-thermal tripscpu-critical8( Ecriticalcpu0-2-top-thermal tripscpu-critical8( Ecriticalcpu0-2-btm-thermal tripscpu-critical8( Ecriticalcpu0-3-top-thermal tripscpu-critical8( Ecriticalcpu0-3-btm-thermal tripscpu-critical8( Ecriticalcpuss0-top-thermal  tripscpuss2-critical8( Ecriticalcpuss0-btm-thermal  tripscpuss2-critical8( Ecriticalmem-thermal  tripstrip-point0_(Ehotmem-critical8( Ecriticalvideo-thermal  tripstrip-point0_(Ehotvideo-critical8( Ecriticalaoss1-thermal tripstrip-point0_(Ehotaoss0-critical8( Ecriticalcpu1-0-top-thermal tripscpu-critical8( Ecriticalcpu1-0-btm-thermal tripscpu-critical8( Ecriticalcpu1-1-top-thermal tripscpu-critical8( Ecriticalcpu1-1-btm-thermal tripscpu-critical8( Ecriticalcpu1-2-top-thermal tripscpu-critical8( Ecriticalcpu1-2-btm-thermal tripscpu-critical8( Ecriticalcpu1-3-top-thermal tripscpu-critical8( Ecriticalcpu1-3-btm-thermal tripscpu-critical8( Ecriticalcpuss1-top-thermal  tripscpuss2-critical8( Ecriticalcpuss1-btm-thermal  tripscpuss2-critical8( Ecriticalaoss2-thermal tripstrip-point0_(Ehotaoss0-critical8( Ecriticalcpu2-0-top-thermal tripscpu-critical8( Ecriticalcpu2-0-btm-thermal tripscpu-critical8( Ecriticalcpu2-1-top-thermal tripscpu-critical8( Ecriticalcpu2-1-btm-thermal tripscpu-critical8( Ecriticalcpu2-2-top-thermal tripscpu-critical8( Ecriticalcpu2-2-btm-thermal tripscpu-critical8( Ecriticalcpu2-3-top-thermal tripscpu-critical8( Ecriticalcpu2-3-btm-thermal tripscpu-critical8( Ecriticalcpuss2-top-thermal  tripscpuss2-critical8( Ecriticalcpuss2-btm-thermal  tripscpuss2-critical8( Ecriticalaoss3-thermal tripstrip-point0_(Ehotaoss0-critical8( Ecriticalnsp0-thermal tripstrip-point0_(Ehotnsp0-critical8( Ecriticalnsp1-thermal tripstrip-point0_(Ehotnsp1-critical8( Ecriticalnsp2-thermal tripstrip-point0_(Ehotnsp2-critical8( Ecriticalnsp3-thermal tripstrip-point0_(Ehotnsp3-critical8( Ecriticalgpuss-0-thermal3 cooling-mapsmap0I Ntripstrip-point0s(Epassivesgpu-critical8( Ecriticalgpuss-1-thermal3 cooling-mapsmap0I Ntripstrip-point0s(Epassivesgpu-critical8( Ecriticalgpuss-2-thermal3 cooling-mapsmap0I Ntripstrip-point0s(Epassivesgpu-critical8( Ecriticalgpuss-3-thermal3 cooling-mapsmap0I Ntripstrip-point0s(Epassivesgpu-critical8( Ecriticalgpuss-4-thermal3  cooling-mapsmap0I Ntripstrip-point0s(Epassivesgpu-critical8( Ecriticalgpuss-5-thermal3  cooling-mapsmap0I Ntripstrip-point0s(Epassivesgpu-critical8( Ecriticalgpuss-6-thermal3  cooling-mapsmap0I Ntripstrip-point0s(Epassivesgpu-critical8( Ecriticalgpuss-7-thermal3  cooling-mapsmap0I Ntripstrip-point0s(Epassivesgpu-critical8( Ecriticalcamera0-thermal  tripstrip-point0_(Ehotcamera0-critical8( Ecriticalcamera1-thermal tripstrip-point0_(Ehotcamera0-critical8( Ecriticalpm8550-thermal3d tripstrip0s(Epassivetrip18(Ehotpm8550ve-2-thermal3d tripstrip0s(Epassivetrip18(Ehotpmc8380-3-thermal3d tripstrip0s(Epassivetrip18(Ehotpmc8380-4-thermal3d tripstrip0s(Epassivetrip18(Ehotpmc8380-5-thermal3d tripstrip0s(Epassivetrip18(Ehotpmc8380-6-thermal3d tripstrip0s(Epassivetrip18(Ehotpm8550ve-8-thermal3d tripstrip0s(Epassivetrip18(Ehotpm8550ve-9-thermal3d tripstrip0s(Epassivetrip18(Ehotpm8010-thermal3d tripstrip0s(Epassivetrip18(Ehotaliases$]/soc@0/geniqup@8c0000/serial@894000$e/soc@0/geniqup@ac0000/serial@a98000audio-codec2qcom,wcd9385-codeceodefault [mw@w@w@w@ $I     PDSbrospmic-glink@2qcom,x1e80100-pmic-glinkqcom,sm8550-pmic-glinkqcom,pmic-glink $y{}connector@02usb-c-connectordualdualports port@0endpointksport@1endpointksport@2endpointksconnector@12usb-c-connectordualdualports port@0endpointksport@1endpointksport@2endpointksconnector@22usb-c-connectordualdualports port@0endpointksport@1endpointksport@2endpointksregulator-edp-3p32regulator-fixed 3VREG_EDP_3P3 B2Z Z2Z Feodefaults#regulator-nvme2regulator-fixed 3VREG_NVME_3P3 B2Z Z2Z eodefaultsregulator-rtmr0-1p152regulator-fixed 3VREG_RTMR0_1P15 B0 Z0 +eodefaultregulator-rtmr0-1p82regulator-fixed 3VREG_RTMR0_1P8 Bw@ Zw@ .eodefaultregulator-rtmr0-3p32regulator-fixed 3VREG_RTMR0_3P3 B2Z Z2Z ' eodefaultregulator-rtmr1-1p152regulator-fixed 3VREG_RTMR1_1P15 B0 Z0 eodefaultsregulator-rtmr1-1p82regulator-fixed 3VREG_RTMR1_1P8 Bw@ Zw@ eodefaultsregulator-rtmr1-3p32regulator-fixed 3VREG_RTMR1_3P3 B2Z Z2Z eodefaultsregulator-rtmr2-1p152regulator-fixed 3VREG_RTMR2_1P15 B0 Z0 eodefaultsregulator-rtmr2-1p82regulator-fixed 3VREG_RTMR2_1P8 Bw@ Zw@ ~eodefaultsregulator-rtmr2-3p32regulator-fixed 3VREG_RTMR2_3P3 B2Z Z2Z eodefaultsregulator-vph-pwr2regulator-fixed 3vph_pwr B8u  Z8u  sregulator-wcn-0p952regulator-fixed 3VREG_WCN_0P95 B~ Z~sregulator-wcn-1p92regulator-fixed 3VREG_WCN_1P9 B Zsregulator-wcn-3p32regulator-fixed 3VREG_WCN_3P3 B2Z Z2Z eodefault sregulator-wwan2regulator-fixed 3SDX_VPH_PWR B2Z Z2Z eodefaultsound2qcom,x1e80100-sndcard ,X1E80100-EVKWooferLeft INWSA WSA_SPK1 OUTTweeterLeft INWSA WSA_SPK2 OUTWooferRight INWSA2 WSA_SPK2 OUTTweeterRight INWSA2 WSA_SPK2 OUTIN1_HPHLHPHL_OUTIN2_HPHRHPHR_OUTAMIC2MIC BIAS2VA DMIC0MIC BIAS3VA DMIC1MIC BIAS3VA DMIC2MIC BIAS1VA DMIC3MIC BIAS1TX SWR_INPUT1ADC2_OUTPUTwcd-playback-dai-link WCD Playbackcodec cpu qplatform wcd-capture-dai-link WCD Capturecodec cpu xplatform wsa-dai-link WSA Playbackcodec0 cpu iplatform va-dai-link VA Capturecodec cpu nplatform usb-1-ss0-sbu-mux2onnn,fsusb42gpio-sbu-mux  !eodefault gportendpointkswcn7850-pmu2qcom,wcn7850-pmu N. <t Lueodefaultregulatorsldo0 3vreg_pmu_rfa_cmnsxldo1 3vreg_pmu_aon_0p59suldo2 3vreg_pmu_wlcx_0p8svldo3 3vreg_pmu_wlmx_0p85swldo4 3vreg_pmu_btcmx_0p85ldo5 3vreg_pmu_rfa_0p8syldo6 3vreg_pmu_rfa_1p2szldo7 3vreg_pmu_rfa_1p8s{ldo8 3vreg_pmu_pcie_0p9ldo9 3vreg_pmu_pcie_1p8 interrupt-parent#address-cells#size-cellsmodelcompatiblechassis-typestdout-pathclock-frequency#clock-cellsphandleclocksclock-multclock-divdevice_typeregenable-methodnext-level-cachepower-domainspower-domain-namescache-levelcache-unifiedcpuentry-methodidle-state-namearm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usremote-endpointinterconnectsqcom,dload-modemboxesmbox-namesshmem#power-domain-cells#interconnect-cellsqcom,bcm-votersinterruptsdomain-idle-statesrangesno-maphwlockssizereusablelinux,cma-defaultopp-hzrequired-oppsinterrupts-extendedqcom,smemqcom,local-pidqcom,remote-pidqcom,entry-name#qcom,smem-state-cellsinterrupt-controller#interrupt-cellsdma-ranges#reset-cells#mbox-cellsdma-channelsdma-channel-mask#dma-cellsiommusstatusclock-namesinterconnect-namesdmasdma-namespinctrl-0pinctrl-namesoperating-points-v2max-speedvddaon-supplyvddwlcx-supplyvddwlmx-supplyvddrfacmn-supplyvddrfa0p8-supplyvddrfa1p2-supplyvddrfa1p8-supplyvdd-supplyvdd33-supplyvdd33-cap-supplyvddar-supplyvddat-supplyvddio-supplyreset-gpiosorientation-switchretimer-switch#phy-cellsvdd3v3-supplyvdd1v8-supplyinterrupt-names#qcom,sensors#thermal-sensor-cellsresetsvdda12-supplyphysreset-namesmode-switchvdda-phy-supplyvdda-pll-supplyreg-namesbus-rangedma-coherentlinux,pci-domainnum-lanesinterrupt-map-maskinterrupt-mapassigned-clocksassigned-clock-ratesphy-nameseq-presets-8gtseq-presets-16gtsopp-peak-kBpsopp-levelclock-output-namesmsi-mapperst-gpioswake-gpiosvddpe-3v3-supplyqcom,4ln-config-sel#hwlock-cellsqcom,gmu#cooling-cellsnvmem-cellsnvmem-cell-namesmemory-regionfirmware-nameqcom,opp-acd-levelopp-supported-hwqcom,qmp#iommu-cells#global-interruptsqcom,smem-statesqcom,smem-state-nameslabelqcom,glink-channelsqcom,non-secure-domainqcom,domainqcom,intents#sound-dai-cellsqcom,protection-domainsound-name-prefixqcom,din-portsqcom,dout-portsqcom,ports-sintervalqcom,ports-offset1qcom,ports-offset2qcom,ports-hstartqcom,ports-hstopqcom,ports-word-lengthqcom,ports-block-pack-modeqcom,ports-block-group-countqcom,ports-lane-controlvdd-1p8-supplyvdd-io-supplyqcom,port-mappingqcom,rx-port-mappingqcom,ports-sinterval-lowqcom,tx-port-mappingvdd-micb-supplyqcom,dmic-sample-rategpio-controller#gpio-cellsgpio-rangespinsfunctiondrive-strengthslew-ratebias-disablebias-bus-holdoutput-highinput-enableqcom,dll-configqcom,ddr-configbus-widthwakeup-sourcesnps,dis_u2_susphy_quirksnps,dis_enblslpm_quirksnps,usb3_lpm_capablesnps,dis-u1-entry-quirksnps,dis-u2-entry-quirkdr_modeusb-role-switchqcom,select-utmi-as-pipe-clkmaximum-speedassigned-clock-parentsdata-laneslink-frequenciespower-supplyqcom,pdc-rangesqcom,eeqcom,channellinux,codeqcom,no-alarmqcom,uefi-rtc-infobits#pwm-cellspower-sourceinput-disableoutput-enablevdd18-supplyvdd3-supplywakeup-parentgpio-reserved-rangesbias-pull-upoutput-lowqcom,cmb-element-bitsqcom,cmb-msrs-numqcom,dsb-element-bitsqcom,dsb-msrs-num#redistributor-regionsredistributor-stridemsi-controller#msi-cellsqcom,tcs-offsetqcom,drv-idqcom,tcs-configqcom,pmic-idvdd-bob1-supplyvdd-bob2-supplyvdd-l1-l4-l10-supplyvdd-l2-l13-l14-supplyvdd-l5-l16-supplyvdd-l6-l7-supplyvdd-l8-l9-supplyvdd-l12-supplyvdd-l15-supplyvdd-l17-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-initial-moderegulator-always-onvdd-l1-supplyvdd-l2-supplyvdd-l3-supplyvdd-s4-supplyvdd-s1-supplyvdd-s2-supplyvdd-s5-supplyframe-numberthermal-sensorstemperaturehysteresispolling-delay-passivetripcooling-deviceserial0serial1qcom,micbias1-microvoltqcom,micbias2-microvoltqcom,micbias3-microvoltqcom,micbias4-microvoltqcom,mbhc-buttons-vthreshold-microvoltqcom,mbhc-headset-vthreshold-microvoltqcom,mbhc-headphone-vthreshold-microvoltqcom,rx-deviceqcom,tx-devicevdd-buck-supplyvdd-rxtx-supplyvdd-mic-bias-supplyorientation-gpiospower-roledata-rolegpioenable-active-highregulator-boot-onvin-supplyaudio-routinglink-namesound-daienable-gpiosselect-gpiosvdddig-supplybt-enable-gpioswlan-enable-gpios